How do the chips on a memory module interrelate?
November 15, 2009 8:12 PM   Subscribe

How is memory typically mapped to the different chips on a DIMM, and what are the typical timing characteristics, broadly speaking? For example, are bytes/words whose address is i mod 8 typically on chip i? In the case of reads, are results returned first from chip 0 (after the RAS and CAS latencies), then promptly on subsequent cycles from each of the next 7 (or 15) chips? How about from other DIMMs on the same motherboard?
posted by espertus to Computers & Internet (3 answers total) 2 users marked this as a favorite
The specification.

I have only glanced at it, but per-byte latency doesn't make sense; the data bus is 64 bits, so you should get them all at the same time. Given that there are byte mask bits, I assume the 8 bytes of a line are stored one per chip.
posted by you at 8:40 PM on November 15, 2009

Best answer: If there are only eight chips on the DIMM, it usually means that each chip provides 8 bits of data for a total of 64 bits. All eight chips are accessed simultaneously providing 64 bits/8 bytes of data to the memory controller. A cache line is usually 64 bytes and you have to replace all 64 bytes at a time, so the memory controller will require 8 consecutive accesses from the chips from adjacent memory locations. The chips are designed to provide these 8 accesses in a burst in which the first access requires the total RAS/CAS delay, but subsequent accesses require only the CAS delay. These 64 bytes replace the entire cache line in cache memory.

When the CPU requires data that is not in cache, the memory controller first retrieves the 8 bytes within the 64 byte block that the CPU needs immediately, then continues the burst to retrieve the remaining bytes within the 64-byte burst. For example if the CPU needs column 3, the DIMM delivers column 3 first, followed by columns 0, 1, 2, 7, 4, 5, 6. The memory controller stuffs these into the proper positions in the 64-byte cache line.

If the DIMM is double-sided, the second set of chips is a completely separate block of memory. The same goes for a second DIMM.
posted by JackFlash at 1:53 AM on November 16, 2009 [1 favorite]

Response by poster: Thank you so much.
posted by espertus at 10:51 AM on November 16, 2009

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