How is memory typically mapped to the different chips on a DIMM, and what are the typical timing characteristics, broadly speaking? For example, are bytes/words whose address is i mod 8 typically on chip i? In the case of reads, are results returned first from chip 0 (after the RAS and CAS latencies), then promptly on subsequent cycles from each of the next 7 (or 15) chips? How about from other DIMMs on the same motherboard?
posted by espertus
on Nov 15, 2009 -