Help understanding clock cycles
April 20, 2009 6:19 PM   Subscribe

I am having a hard time understanding clock cycles and sequential logic. I think I understand gates, etc but the clock really confuses me.

Specifically, I don't understand the following statement: "all state changes occur on a clock edge". What causes these edges? Does the state chance cause the clock signal to change or is it the other way around? As you can probably tell, I'm sort of lost. I've been looking around for tutorials, but they're usually pretty advanced and don't help me with this basic part.
posted by Raichle to Computers & Internet (14 answers total) 6 users marked this as a favorite
 
IIRC, the clock in the chip is an electronic pulse, meaning that it emits a rising, then falling, then rising, then falling, etc. pulse of electricity that's extremely regular. It's not a sine wave, it's like turning a tap all the way on for a second, then all the way off for a second, then all the way on... in other words, it's a series of hard-edged plateaus. The edge is the rising and falling, rather than the top of the plateaus.

The architecture of the chip keys all state changes to occur with the occurrence of a clock edge in order to synchronize everything, giving it a deterministic logic. I don't think it's correct to say the that state change is caused by the clock edge, more like the clock edge is a necessary condition of a state change, since all state changes occur by design on the occurrence of a clock cycle edge.

If you've played any turn based game, it's just like that. Keying events to a clock edge is just separating all state changes into discrete, timed segments.
posted by fatbird at 6:28 PM on April 20, 2009


The clock signal causes the state of sequential logic to change (or maybe not change, depending on the input to the logic, of course). The typical digital system will have one or more clock signals input to it via an oscillator, a crystal, a PLL, or possibly something more exotic.

I imagine your question is more complicated than this, so please feel free to clarify. I do digital logic design as my profession, so I enjoy topical questions!
posted by saeculorum at 6:29 PM on April 20, 2009



A basic model is to think of it in terms of two kinds of logic components: Flip-flops and Plain old gates (AND, OR, NOR, NAND, NOT, XOR, Mutexes, etc...)

The Plain old gates operate asynchronously-- they just do their thing, so when their inputs get changed, the output gets changed as fast as it can. This isn't instantaneous, it takes some time ("propogation delay",) but this all happens without a clock.

But, if you want your circuit to have any kind of memory-- i.e., be "stateful", you need components which can remember what inputs they had at a particular point in time. A flip flop is such a component. There are multiple kinds, but an example one has a single input and a single output, that also connects to the clock. When the clock changes from High to low, or from low to high, the flip-flop gate makes its output match its input. Now, the new value is the 'state' of the flip flop. i.e., it's been locked in.

So, the clock turned a voltage level (that was already there) into 'state' in the flipflop. Since the flipflop remembering it's input (and presenting it as output) only occurs on a clock edge, it could be said that 'all state changes occur on a clock edge.'
posted by blenderfish at 6:48 PM on April 20, 2009


Response by poster: So, I guess I'm having a hard time explaining my question because I don't really know what I'm missing here.

So, looking at a D Latch, for example. When the clock is asserted, D replaces Q. If the value of D changes and the clock is still asserted, since this is "transparent" does this mean the value of Q will change even though the clock is not on an edge?

And, is it correct to say that this does not happen in a "flip-flop" since changes can only occur on "clock-edges".
posted by Raichle at 6:51 PM on April 20, 2009


s/Mutexes/Multiplexers
s/it's/its

Must preview moar.
posted by blenderfish at 6:52 PM on April 20, 2009


Think flipflops, not latches.
posted by blenderfish at 6:58 PM on April 20, 2009


Response by poster: s/moar/more/g :)

What do you mean by "think flipflops, not latches"? I'm looking at both for comparison to try to figure this stuff out.
posted by Raichle at 7:01 PM on April 20, 2009


As a note, latches are very rarely used in digital design. More than a few companies completely ban their use. As blenderfish suggests, it may not be worthwhile to even think about them.

That said, your statement about the difference between latches and flip-flops is completely correct. Latches are open for the whole clock assertion period (with a clock with 50/50 high/low duty cycle, that's half the time - however, not all clocks have a 50/50 duty cycle). Flip-flops are only open for the clock edge. As a result, flip-flops only change state on a clock edge. Hence, the origin of the statement "in a synchronous system, everything happens on a clock edge."

Bonus trivia: the textbook implementation of a flip-flops is with two latches - a "master" and a "slave" latch. One "opens" on the clock being high and one "opens" on the clock being low. A bit of cleverness in creating those latches allows both to be open for the instant when the clock transitions from low to high (or high to low).
posted by saeculorum at 7:03 PM on April 20, 2009


Saeculorum breaks it down well.

A couple other random thoughts:

If you really, really want to reconcile your statement with latches, another way of thinking about it might be that "while a latch open (i.e., is transparent,) it doesn't have any state." Since no state exists, no state transition can occur.

A 'plain old' gate like an AND or XOR or NOT never has state. Sure, you can measure it's current output voltage with a logic probe, but that isn't state. It would cease if the input changed.

An open latch is like two NOT gates in a row. No state.

(Keep in mind that the definition of 'state' is more of a concept than a physical phenomenon.)
posted by blenderfish at 7:13 PM on April 20, 2009


Response by poster: I'm just trying to learn the theory right now and sorta hope to never have to deal with this stuff in the future. That's why I was learning about latches, but I understand your points. Thanks for the help.
posted by Raichle at 7:56 PM on April 20, 2009


Ok, so, to understand clocks, you need to understand the difference between edge triggering and level clocking. Quoth Malvino, "When a circuit is edge-triggered, the output can change only on the rising (or falling) edge of the clock But when the circuit is level-clocked, the output can change while the clock is high (or low) with edge triggering, the output can change only at one instant during the clock cycle; with level clocking, the output can change during an entire half cycle of the clock."

You say that you're looking at D latches, right? This might help._ indicates LOW while - indicates HIGH...both clocks remain the same

LEVEL CLOCKED


CLOCK:__________-----------___________------------___________-------
D:_______________-----------______----______---____-----_____---
Q: ______________----------------------------___---_____________-----


POSITIVELY EDGE CLOCKED

CLOCK:__________-----------___________------------___________-------
D:____________--___-----____--------___---____-----_____---_______
Q: ________________________________-----------------------------____



This formatting isn't the best, so hopefully you can make sense of it. In level clocking, the WHOLE clock 0 or 1 matters...in edge triggered, the value at the instant of change is what matters.
posted by vas deference at 9:47 PM on April 20, 2009


In theory, a state change in a synchronous component occurs at the instant the clock input makes the transition from low to high (for positive edge triggered registers) or high to low (for negative edge triggered registers). In practice, there's no such thing as an instant; it takes a small but definite amount of time for the clock signal to get from low to high and back again. There is no such thing, in the real world, as a perfect square wave.

So a natural followup question that occurred to me when I was first learning this stuff is "what happens if an input signal changes at the same time as the clock does?"

The short answer: nothing good!

The long answer: this is why clocked components have specified setup and hold times, with respect to the active clock edge, for their non-clock inputs.

Setup time is a defined period before the clock edge during which no change in the non-clock inputs is allowed. Hold time is a defined period after the clock edge during which no change in the non-clock inputs is allowed.

If there is in fact a transition on a non-clocked input that violates the setup or hold time, the resulting state of the register will be undefined. It might even be worse than undefined - it may be indeterminate: for a significant number of nanoseconds, the output signal might be at some analog voltage level in between those defined to be a definite 0 or a definite 1. This is called a metastable state.

If a register is supposed to sample and capture the state of some external signal - i.e. one that's not generated inside a logic block clocked by the same clock as that register, so that signal transitions can occur at any time with respect to the register clock - it's good practice to use two registers in a chain to do that job. Both registers can be fed from a common clock, or you can feed the first one from the inversion of the second one's clock to minimize total delay.

The first register will suffer the occasional metastable, but this will have settled into one of the stable states by the time the next clocking edge arrives - meaning that the second register, whose output stability and timing you actually care about, will never see violations of setup and hold times on its input and will never present a metastable output to the rest of your logic.
posted by flabdablet at 11:44 PM on April 20, 2009


So, looking at a D Latch, for example. When the clock is asserted, D replaces Q. If the value of D changes and the clock is still asserted, since this is "transparent" does this mean the value of Q will change even though the clock is not on an edge?

And, is it correct to say that this does not happen in a "flip-flop" since changes can only occur on "clock-edges".


Sounds like you got it. In the latch, whatever is on the input shows up on the output as long as the 'clock' (or 'enable') is high. In the flip-flop, the output gets set to the input on the clock edge.

Here's a more advanced question:
What happens to the output of a flip-flop if the input changes at the same time as the clock edge?

The answer: you don't know. Flip-flops are only reliable if the input is stable around the time that the clock edge comes. They have 'setup' and 'hold' requirements--the time before and after the clock that the data needs to be stable.

If you understand this, then you know the basics really well. The reason a particular Intel processor can run at 2.5GHz and not 2.6GHz is because somewhere in the chip the data doesn't get to a flip-flop in time, so the 'setup' requirement ends up being violated, leading to unpredictable output, and eventual processor crashing.
posted by eye of newt at 10:12 AM on April 21, 2009


or what flabdablet said
posted by eye of newt at 10:14 AM on April 21, 2009


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